26.4.5 CCPx Time Base Register
Note:
- TMR[31:16] will be available
when operating in a valid 32-Bit Operating mode or the Dual 16-Bit Time Base
mode. TMR[31:16] will read as ‘
0’ when operating in all other modes. - All writes to CCPxTMR are buffered for atomic update operation. The CCPxTMR value is not updated until the uppermost byte of the timer is written. If the timer clock source is asynchronous, user software must monitor the status bits to ensure the prior write has completed before performing another write.
| Name: | CCPxTMR |
| Offset: | 0x1B10, 0x1B40, 0x1B70, 0x1BA0, 0x1BD0, 0x1C00, 0x1C30, 0x1C60, 0x1C90 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TMR[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TMR[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TMR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |