26.4.6 CCPx Period Register
Note:
- For Dual 16-Bit Timer mode,
the PR[31:16] bits set the count period for the second 16-bit timer. For
32-bit timer operation, the PR[31:0] bits set the count period for the
single 32-bit timer. On a device Reset, the module will reset to a Dual
16-Bit Timer mode. The CCPxPR Reset value of FFFFFFFF provides the maximum
count period for both timers. The PR[31:16] bits are not available in 16-Bit
Output Compare modes and will read as ‘
0’. The PR[31:0] bits are not available in 32-Bit Output Compare modes and will read as ‘0’.
| Name: | CCPxPR |
| Offset: | 0x1B14, 0x1B44, 0x1B74, 0x1BA4, 0x1BD4, 0x1C04, 0x1C34, 0x1C64, 0x1C94 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PR[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PR[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |