22.4.8 I2Cx Control Register

Note:
  1. Automatically cleared to ‘0’ at the beginning of client transmission; automatically cleared to ‘0’ at the end of client reception.
  2. Automatically cleared to ‘0’ at the beginning of client transmission.
  3. When EPSZE is enabled, Smart mode (SMEN=1), clock stretching (STREN=1) and EOP function (EOPSC= “10” or “01” ) should be enabled.
  4. In Host mode , when ACKC != 00, hardware will automatically set the ACKEN (I2CxCON1[4]) bit.
  5. In Host mode, this bit will be used by PSZ(I2CxCON2[15:0]) to count the data bytes.
  6. In Client mode, this bit is used for TX/RX interrupt generation.

    If ‘1’, an Interrupt is generated only for data bytes. If ‘0’, an Interrupt is generated for both address and data bytes.

  7. In Client mode, it should set the ND/A to ‘1’ before enabling transfers through DMA for data transfer.
  8. The packet size should be excluding of address byte(s). It should not be changed on fly and should be changed when the bus is in an Idle state.
  9. In Host mode, the EOPSC and ND/A bits control the PSZ to decrement.
  10. For the host, the software has to clear the CRC calculator by setting I2CxCON2.PECC to “11” for a new data frame transaction.
  11. To use the Auto-Append mode, the PECC needs to be set to “01” at least one data byte earlier than the CRC byte of data.

Legend: HC = Hardware Clearable bit

Name: I2CxCON2
Offset: 0x189C, 0x18EC, 0x193C

Bit 3130292827262524 
 AMODE[1:0]PECC[1:0]BSCLTEHBCTECBCTEEPSZE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ACKC[1:0]HNACKIGNEOPSC[1:0]ND/ASMENBITE 
Access R/WR/WR/WR/W/HCR/W/HCR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PSZ[15:8] 
Access R/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HC 
Reset 00000000 
Bit 76543210 
 PSZ[7:0] 
Access R/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HCR/W/HC 
Reset 00000001 

Bits 31:30 – AMODE[1:0] Address Mode bits

ValueDescription
11 Reserved
10 The client responds to the range of addresses between and including I2CxADD and I2CxMSK. I2CxMSK is the upper limit.
01 The client responds to the two unique addresses in I2CxADD and I2CxMSK.
00 I2CxMSK is used as a mask to the I2CxADD register.

Bits 29:28 – PECC[1:0]  PEC Control bits(10,11)

ValueDescription
11 PEC Reset
10 PEC append is disabled. CRC-8 calculator will be active.

On a read request (receive), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) at EOP.

On a write request (transmit), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) at EOP.
01

Calculated CRC-8 is appended at the end of a packet.

On a read request (receive), calculated CRC-8 is copied into CCRC (I2CxPEC[15:8]) and received CRC will be copied into RCRC (I2CxPEC[7:0]) at EOP.

On a write Request (transmit), calculated CRC-8 will be automatically appended and also copied into CCRC (I2CxPEC[15:8]) at the end of the data transmission. PEC will be get reset after appending.
00 PEC disabled

Bit 27 – BSCLTE Bus SCL Time-out Enable bit

ValueDescription
1 SCL low time-out enabled
0 SCL low time-out disabled

Bit 26 – HBCTE Host Bus SCL Cumulative (Extended time) Low Time-out Enable bit

ValueDescription
1 SCL Cumulative low extended time-out enable
0 SCL Cumulative low extended time-out disable

Bit 25 – CBCTE Client Bus SCL Cumulative (Extended time) Low Time-out Enable bit

ValueDescription
1 SCL Cumulative low extended time-out enable
0 SCL Cumulative low extended time-out disable

Bit 24 – EPSZE  Extended Packet Size Enable bit (Valid for Client Receive mode only)(3)

ValueDescription
1 Extended packet size enabled after EOP=1
0 Extended packet size disable

Bits 23:22 – ACKC[1:0]  ACK Control bits(4)

ValueDescription
11

Host: ACK all the bytes except the CRC byte; for the CRC byte, a NACK will be sent .

Client: ACK all the bytes and for the last byte, which is the CRC byte, a ACK or NACK based on CRC result.
  • If the CRC is 0, an ACK is sent.
  • If the CRC is non-zero, a NACK is sent (to be used only on PECC[1:0] = “01” Auto-Append mode).
10 ACK all the bytes, and the last byte will be NACKed (to be used only for last packet).
01 ACK all bytes including end of packet (to be used for extended packets).
00

ACK/NACK based on ACKDT and BOEN (client).

ACK/NACK based on ACKEN and ACKDT (host).

Bit 21 – HNACKIGN Host NACK Response Ignore Control bit

ValueDescription
1 Host treats all NACK responses as an ACK.
0 Normal operation; host treats NACK responses as a NACK only.

Bits 20:19 – EOPSC[1:0] End of Packet Status Control bits

ValueDescription
11 Reserved
10 I2CxSTAT2.EOP will be set after the data bytes and PEC.
01 I2CxSTAT2.EOP will be set after the data bytes.
00 The end of packet function is disabled.

Bit 18 – ND/A  Next Data/Address Byte Transmission bit(5,6,7)

ValueDescription
1 Next transmission is a data byte transmission.
0 Next transmission is an address byte transmission.

Bit 17 – SMEN Smart Mode Enable bit

ValueDescription
1 Smart mode is enabled.
0 Smart mode is disabled.

Bit 16 – BITE Bus Idle Time-out Enable bit

ValueDescription
1 Bus idle time-out enable
0 Bus idle time-out disabled

Bits 15:0 – PSZ[15:0]  Packet Size bits(8,9)

Sets the size of the packet to transfer/receive; the valid range is from 0 to 65535 bytes. Use I2CxCONC.PSZ=0 for the SMBus Quick Command protocol,