22.4.1 I2Cx Control Register
- Automatically cleared to
‘
0’ at the beginning of client transmission; automatically cleared to ‘0’ at the end of client reception. - Automatically cleared to
‘
0’ at the beginning of client transmission. - This bit must be set before any I2C operations can be performed. This bit should be set in a separate instruction from any of the other enable bits.
- 16 peripheral clock cycles should be waited before performing any operation.
Legend: HC = Hardware Clearable bit
| Name: | I2CxCON1 |
| Offset: | 0x1880, 0x18D0, 0x1920 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SMBEN[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | SCLREL | STRICT | A10M | DISSLW | ||||
| Access | R/W | R/W | R/W/HC | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GCEN | STREN | ACKDT | ACKEN | RCEN | PEN | RSEN | SEN | ||
| Access | R/W | R/W | R/W | R/W/HC/HS | R/W/HC/HS | R/W/HC | R/W/HC | R/W/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 25:24 – SMBEN[1:0] SMBus Input Levels Enable bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
Enable SMBus 3.0 input threshold voltage specification. |
| 01 |
Enable SMBus 2.0 input threshold voltage specification. |
| 00 |
Enable I2C input threshold voltage specification (disable SMBus specific input). |
Bit 22 – PCIE Stop Condition Interrupt Enable bit (Client mode only)
| Value | Description |
|---|---|
1 |
Enables interrupt on detection of Stop condition. |
0 |
Stop detection interrupts are disabled. |
Bit 21 – SCIE Start Condition Interrupt Enable bit (Client mode only)
| Value | Description |
|---|---|
1 |
Enables interrupt on detection of Start or Restart conditions. |
0 |
Start detection interrupts are disabled. |
Bit 20 – BOEN Buffer Overwrite Enable bit (Client mode only)
| Value | Description |
|---|---|
1 |
I2CxRCV is updated and an ACK is generated for a received
address/data byte, ignoring the state of the I2COV bit only if RBF bit =
|
0 |
I2CxRCV is only updated when I2COV is clear. |
Bit 19 – SDAHT SDAx Hold Time Selection bit
| Value | Description |
|---|---|
1 |
Minimum of 300 ns hold time on SDAx after the falling edge of SCLx. |
0 |
Minimum of 100 ns hold time on SDAx after the falling edge of SCLx. |
Bit 18 – SBCDE Mode Bus Collision Detect Enable bit (Client mode only)
If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a High state, the BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
| Value | Description |
|---|---|
1 |
Enables client bus collision interrupts. |
0 |
Client bus collision interrupts are disabled. |
Bit 17 – AHEN Client Address Hold Enable bit
| Value | Description |
|---|---|
1 |
Following the eighth falling edge of SCLx for a matching received address byte, the SCLREL bit (I2CxCON1[12]) will be cleared and the SCLx will be held low. |
0 |
Address holding is disabled. |
Bit 16 – DHEN Client Data Hold Enable bit
| Value | Description |
|---|---|
1 |
Following the eighth falling edge of SCLx for a received data byte, client hardware clears the SCLREL bit (I2CxCON1[12]) and SCLx is held low. |
0 |
Data holding is disabled. |
Bit 15 – ON I2Cx Enable bit (writable from software only)(3,4)
| Value | Description |
|---|---|
1 |
Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins. |
0 |
Disables the I2Cx module; all I2C pins are controlled by port functions. |
Bit 13 – SIDL I2Cx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when the device enters Idle mode. |
0 |
Continues module operation in Idle mode. |
Bit 12 – SCLREL SCLx Release Control bit (I2C Client mode only)(1)
If STREN = 1:(2)
User software may write ‘0’ to initiate a clock stretch and
write ‘1’ to release the clock. Hardware clears at the beginning of
every client data byte transmission. Hardware clears at the end of every client
address byte reception. Hardware clears at the end of every client data byte
reception.
If STREN = 0:
User software may only write ‘1’ to release the clock. Hardware
clears at the beginning of every client data byte transmission. Hardware clears at
the end of every client address byte reception.
| Value | Description |
|---|---|
1 |
Releases the SCLx clock. |
0 |
Holds the SCLx clock low (clock stretch). |
Bit 11 – STRICT I2Cx Strict Reserved Address Rule Enable bit
| Value | Description |
|---|---|
1 |
Strict reserved addressing is enforced for reserved addresses. (In Client mode) – The device doesn’t respond to reserved address space, and addresses falling in that category are NACKed. (In Host mode) – The device is allowed to generate addresses with reserved address space. |
0 |
Reserved addressing would be Acknowledged. (In Client mode) – The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK. (In Host mode) – Reserved |
Bit 10 – A10M 10-Bit Client Address Flag bit
| Value | Description |
|---|---|
1 |
I2CxADD is a 10-bit client address. |
0 |
I2CxADD is a 7-bit client address. |
Bit 9 – DISSLW Slew Rate Control Disable bit
| Value | Description |
|---|---|
1 |
Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode). |
0 |
Slew rate control is enabled for High-Speed mode (400 kHz). |
Bit 7 – GCEN General Call Enable bit (in I2C Client mode only)
| Value | Description |
|---|---|
1 |
Enables an interrupt when a general call address is received in I2CxRSR; a module is enabled for reception. |
0 |
The general call address is disabled. |
Bit 6 – STREN SCLx Clock Stretch Enable bit
In I2C Client mode only; used in conjunction with the SCLREL bit.
| Value | Description |
|---|---|
1 |
Enables clock stretching. |
0 |
Disables clock stretching. |
Bit 5 – ACKDT Acknowledge Data bit
In I2C Host mode during Host Receive mode. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
In I2C Client mode when AHEN = 1 or DHEN =
1. The value that the client will transmit when it initiates an
Acknowledge sequence at the end of an address or data reception.
| Value | Description |
|---|---|
1 |
NACK is sent, |
0 |
ACK is sent, |
Bit 4 – ACKEN Acknowledge Sequence Enable bit
In I2C Host mode only; applicable during Host Receive mode.
| Value | Description |
|---|---|
1 |
Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. |
0 |
Acknowledge sequence is Idle. |
Bit 3 – RCEN Receive Enable bit (in I2C Host mode only)
| Value | Description |
|---|---|
1 |
Enables Receive mode for I2C; automatically cleared by hardware at end of 8-bit receive data byte. |
0 |
Receive sequence is not in progress. |
Bit 2 – PEN Stop Condition Enable bit (in I2C Host mode only)
| Value | Description |
|---|---|
1 |
Initiates Stop condition on SDAx and SCLx pins. |
0 |
Stop condition is Idle. |
Bit 1 – RSEN Restart Condition Enable bit (in I2C Host mode only)
| Value | Description |
|---|---|
1 |
Initiates Restart condition on SDAx and SCLx pins. |
0 |
Restart condition is Idle. |
Bit 0 – SEN Start Condition Enable bit (in I2C Host mode only)
| Value | Description |
|---|---|
1 |
Initiates Start condition on SDAx and SCLx pins. |
0 |
Start condition is Idle. |