22.4.18 I2C Host Input Delay Compensation Register

Note:
  1. Default value, assumed UPB clock is 50 MHz and path delay is 360 ns with 2.3V and 1.1K pull-up resistance (worst case).
Name: I2CxHDLYC
Offset: 0x18CC, 0x191C, 0x196C

Bit 3130292827262524 
 HIDLYCEN        
Access R/W 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 HIDLYC[15:8] 
Access  
Reset 00000000 
Bit 76543210 
 HIDLYC[7:0] 
Access  
Reset 00000000 

Bit 31 – HIDLYCEN I2C Host Input Delay Compensation Enable bit

ValueDescription
1 Programmable hardware host input delay compensation is enabled (default).
0 Fixed hardware host input delay compensation is used.

Bits 15:0 – HIDLYC[15:0] Host Input Delay Compensation Value bits

These bits are used to compensate for input path delays for the Host mode sampling point.
ValueDescription
1111 HIDLYC Value x I2C UPB CLK TIME
0010 18 x I2C UPB CLK TIME (default)(1)
0001 1 x I2C UPB CLK TIME
0000 0 x I2C UPB CLK TIME