22.4.2 I2Cx Status Register

Legend: C = Clearable bit, HS = Hardware Settable bit, HSC = Hardware Settable/Clearable bit

Name: I2CxSTAT1
Offset: 0x1884, 0x18D4, 0x1924

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ACKSTATTRSTATACKTIM  BCLGCSTATADD10 
Access R/HSCR/HSCR/HSCR/C/HSCR/HSCR/HSC 
Reset 000000 
Bit 76543210 
 IWCOLI2COVD/APSR/WRBFTBF 
Access R/C/HSR/C/HSR/HSCR/HSCR/HSCR/HSCR/HSCR/HSC 
Reset 00000000 

Bit 15 – ACKSTAT Acknowledge Status bit (updated in all Host and Client modes)

ValueDescription
1

Acknowledge was not received from client.

0

Acknowledge was received from client.

Bit 14 – TRSTAT  Transmit Status bit (when operating as I2C host; applicable to host transmit operation)

ValueDescription
1

Host transmit is in progress (eight bits + ACK).

0

Host transmit is not in progress.

Bit 13 – ACKTIM  Acknowledge Time Status bit (valid in I2C Client mode only)

ValueDescription
1

Indicates I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCLx clock.

0

Not an Acknowledge sequence, cleared on ninth rising edge of SCLx clock.

Bit 10 – BCL  Bus Collision Detect bit

(Host/Client mode; cleared when I2C module is disabled, I2CEN = 0)
ValueDescription
1

A bus collision has been detected during a host or client transmit operation.

0

No bus collision has been detected.

Bit 9 – GCSTAT General Call Status bit (cleared after Stop detection)

ValueDescription
1

General call address was received.

0

General call address was not received.

Bit 8 – ADD10 10-Bit Address Status bit (cleared after Stop detection)

ValueDescription
1

10-bit address was matched.

0

10-bit address was not matched.

Bit 7 – IWCOL I2Cx Write Collision Detect bit

ValueDescription
1

An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared in software.

0

No collision

Bit 6 – I2COV I2Cx Receive Overflow Flag bit

ValueDescription
1 A byte was received while the I2CxRCV register is still holding the previous byte.
0 No overflow

Bit 5 – D/A  Data/Address bit (when operating as I2C Client)

ValueDescription
1

Indicates that the last byte received was data.

0

Indicates that the last byte received or transmitted was an address.

Bit 4 – P Stop bit

Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.

ValueDescription
1

Indicates that a Stop bit has been detected last.

0

Stop bit was not detected last.

Bit 3 – S I2Cx Start bit

Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.

ValueDescription
1

Indicates that a Start (or Repeated Start) bit has been detected last.

0

Start bit was not detected last.

Bit 2 – R/W  Read/Write Information bit (when operating as I2C Client)

ValueDescription
1

Read: Indicates the data transfer is the output from the client.

0

Write: Indicates the data transfer is the input to the client.

Bit 1 – RBF Receive Buffer Full Status bit

ValueDescription
1

Receive is complete; I2CxRCV is full.

0

Receive is not complete; I2CxRCV is empty.

Bit 0 – TBF Transmit Buffer Full Status bit

ValueDescription
1

Transmit is in progress; I2CxTRN is full (eight bits of data).

0

Transmit is complete; I2CxTRN is empty.