Floating-Point Control Register (FCR)

The FCR is comprised of the following bit fields as defined in FCR.

Floating-Point Exception Mask bits, FCR [6:0]: Each Exception Mask bit corresponds to an Exception Status flag in the FSR. The Mask bit must be clear to allow the exception event to generate an interrupt to the CPU. The Underflow Mask bit (FCR.UDFM) is also used as part of the Flush-to-Zero (FTZ) mode enable as discussed in Flush-To-Zero (FTZ).

Floating-Point Rounding Mode Control bits, FCR [9:8]: These bits define the Global IEEE 754 Compatible Rounding mode used by the FPU instruction. See Rounding Modes.

Floating-Point Subnormal Override Mode Control bits, FCR [11:10]: These bits enable the Subnormals-Are-Zero (SAZ) and Flush-to-Zero (FTZ) Subnormal Override modes supported by the FPU.