62.14 GMAC PHY Maintenance Register
The PHY Maintenance Register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit 2 is set in the Network Status Register. It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
During this time, the MSB of the register is output on the GMDIO pin and the LSB updated from the GMDIO pin with each MDC cycle. This causes transmission of a PHY management frame on the GMDIO pin. See Section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. To write clause 45 PHYs, bits 31:28 should be written as 0x0001. See the table below.
| PHY | Access | Bit Value | |||
|---|---|---|---|---|---|
| WZO | CLTTO | OP[1] | OP[0] | ||
| Clause 22 | Read | 0 | 1 | 1 | 0 |
| Write | 0 | 1 | 0 | 1 | |
| Clause 45 | Read | 0 | 0 | 1 | 1 |
| Write | 0 | 0 | 0 | 1 | |
| Read + Address | 0 | 0 | 1 | 0 | |
For a description of MDC generation, see GMAC Network Configuration Register.
| Name: | GMAC_MAN |
| Offset: | 0x034 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WZO | CLTTO | OP[1:0] | PHYA[4:1] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHYA[0] | REGA[4:0] | WTN[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – WZO Write ZERO
Must be written with 0.
Bit 30 – CLTTO Clause 22 Operation
| Value | Description |
|---|---|
| 0 | Clause 45 operation |
| 1 | Clause 22 operation |
Bits 29:28 – OP[1:0] Operation
| Value | Description |
|---|---|
| 01 | Write |
| 10 | Read |
Bits 27:23 – PHYA[4:0] PHY Address
Bits 22:18 – REGA[4:0] Register Address
Specifies the register in the PHY to access.
Bits 17:16 – WTN[1:0] Write Ten
Must be written to 10.
Bits 15:0 – DATA[15:0] PHY Data
For a write operation this field is written with the data to be written to the PHY. After a read operation this field contains the data read from the PHY.