62.132 GMAC Receive Queue Upper Buffer Address RegisterName: GMAC_RQUBAOffset: 0x4D4Reset: 0x00000000Property: Read/WriteBit 3130292827262524 RQUBA[31:24] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 2322212019181716 RQUBA[23:16] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 15141312111098 RQUBA[15:8] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 76543210 RQUBA[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bits 31:0 – RQUBA[31:0] Receive Queue Upper Buffer Address Upper 32 bits of receive buffer descriptor queue base address.
Bit 3130292827262524 RQUBA[31:24] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 2322212019181716 RQUBA[23:16] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 15141312111098 RQUBA[15:8] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 76543210 RQUBA[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000
Bits 31:0 – RQUBA[31:0] Receive Queue Upper Buffer Address Upper 32 bits of receive buffer descriptor queue base address.