62.10 GMAC Interrupt Status Register

This register indicates the source of the interrupt. In order that the bits of this register read 1, the corresponding interrupt source must be enabled in the mask register. If any bit is set in this register, the GMAC interrupt signal will be asserted in the system.

Name: GMAC_ISR
Offset: 0x024
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
   TSUTIMCOMPWOLRXLPISBCSRIPDRSFTPDRQFT 
Access RRRRRR 
Reset 000000 
Bit 2322212019181716 
 PDRSFRPDRQFRSFTDRQFTSFRDRQFR   
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
  PFTRPTZPFNZHRESPROVR   
Access RRRRR 
Reset 00000 
Bit 76543210 
 TCOMPTFCRLEXTURTXUBRRXUBRRCOMPMFS 
Access RRRRRRRR 
Reset 00000000 

Bit 29 – TSUTIMCOMP TSU Timer Comparison (cleared on read)

Indicates when the TSU timer count value is equal to programmed value.

Bit 28 – WOL Wake On LAN

WOL interrupt. Indicates a WOL event has been received.

Bit 27 – RXLPISBC Receive LPI indication Status Bit Change (cleared on read)

Receive LPI indication status bit change.

Bit 26 – SRI TSU Seconds Register Increment (cleared on read)

Indicates the register has incremented.

Bit 25 – PDRSFT PDelay Response Frame Transmitted (cleared on read)

Indicates a PTP pdelay_resp frame has been transmitted.

Bit 24 – PDRQFT PDelay Request Frame Transmitted (cleared on read)

Indicates a PTP pdelay_req frame has been transmitted.

Bit 23 – PDRSFR PDelay Response Frame Received (cleared on read)

Indicates a PTP pdelay_resp frame has been received.

Bit 22 – PDRQFR PDelay Request Frame Received

Indicates a PTP pdelay_req frame has been received.

Bit 21 – SFT PTP Sync Frame Transmitted (cleared on read)

Indicates a PTP sync frame has been transmitted.

Bit 20 – DRQFT PTP Delay Request Frame Transmitted (cleared on read)

Indicates a PTP delay_req frame has been transmitted. (cleared on read)

Bit 19 – SFR PTP Sync Frame Received (cleared on read)

Indicates a PTP sync frame has been received.

Bit 18 – DRQFR PTP Delay Request Frame Received (cleared on read)

Indicates a PTP delay_req frame has been received.

Bit 14 – PFTR Pause Frame Transmitted (cleared on read)

Indicates a pause frame has been successfully transmitted after being initiated from the Network Control register.

Bit 13 – PTZ Pause Time Zero (cleared on read)

Set when either the Pause Time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.

Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received (cleared on read)

Indicates a valid pause has been received that has a non-zero pause quantum field.

Bit 11 – HRESP System Bus Error (cleared on read)

Set when the DMA block sees a system bus error.

Bit 10 – ROVR Receive Overrun (cleared on read)

Set when the receive overrun status bit is set.

Bit 7 – TCOMP Transmit Complete (cleared on read)

Set when a frame has been transmitted.

Bit 6 – TFC Transmit Frame Corruption Due to System Bus Error (cleared on read)

Set if an error occurs while midway through reading transmit frame from the system bus, including system bus error and buffers exhausted mid frame.

Bit 5 – RLEX Retry Limit Exceeded or Late Collision (cleared on read)

Transmit error. Late collision will only cause this status bit to be set in Gigabit mode, as a retry is not attempted.

Bit 4 – TUR Transmit Underrun (cleared on read)

This interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable.

This interrupt is set if a transmitter status write back has not completed when another status write back is attempted.

This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the system bus was not granted in time for further data, or because a system bus error response was returned, or because the used bit was read.

Bit 3 – TXUBR TX Used Bit Read (cleared on read)

Set when a transmit buffer descriptor is read with its used bit set.

Bit 2 – RXUBR RX Used Bit Read (cleared on read)

Set when a receive buffer descriptor is read with its used bit set.

Bit 1 – RCOMP Receive Complete (cleared on read)

A frame has been stored in memory.

Bit 0 – MFS Management Frame Sent (cleared on read)

The PHY Maintenance Register has completed its operation.