62.20 GMAC System Bus Max Pipeline Register
| Name: | GMAC_AMP |
| Offset: | 0x054 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| USE_FROM | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AW2W_MAX_PIPELINE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AR2R_MAX_PIPELINE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 16 – USE_FROM Address Write Bus to Write Data Bus Maximum Pipeline
| Value | Name | Description |
|---|---|---|
| 0 | AW2W | Operates the AW2W_MAX_PIPELINE field between AW to W channel. |
| 1 | AW2B | Operates the AW2W_MAX_PIPELINE field between AW to B channel. |
Bits 15:8 – AW2W_MAX_PIPELINE[7:0] Address Write Bus to Write Data Bus Maximum Pipeline
Defines the maximum number of outstanding write requests that can be issued by the DMA via the AW channel. This is effectively the write issuing capability.