62.1 GMAC Network Control Register


Bit	31	30	29	28	27	26	25	24
		IFGQAVCRED		MIIONRGMII	OSSCORR	EXTSELRQEN	PFCCTL	OSSMODE
Access		R/W		R/W	R/W	R/W	R/W	R/W
Reset		0		0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		STUDPOFFSET		PTPUNIENA	TXLPIEN	FNP	TXPBPF	ENPBPR
Access		R/W		R/W	R/W	R/W	R/W	R/W
Reset		0		0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	SRTSM			TXZQPF	TXPF	THALT	TSTART	BP
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	WESTAT	INCSTAT	CLRSTAT	MPE	TXEN	RXEN	LBL
Access	R/W	W	W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0

Bit 30 – IFGQAVCRED Credit-Based Shaping Algorithm Modification

Value	Description
0	No modification of the CBS algorithm.
1	Modifies the CBS algorithm so the IFG/IPG associated with a transmit frame counts towards its 802.1Qav credit.

Bit 28 – MIIONRGMII MII Control

Value	Description
0	Disables MII operation.
1	Enables MII operation when GMAC_UR.MIM=0.

Bit 27 – OSSCORR OSS Correction Field

1588 One Step Correction field update. Set this bit high to update the correction field of PTP 1588 version 2 sync frames by adding current TSU timer value.

Bit 26 – EXTSELRQEN External Selection of Receive Queue Enable

Value	Description
0	Disables external selection of receive queue.
1	Enables external selection of receive queue.

Bit 25 – PFCCTL Multiple PFC Pause Quantum Enable

Value	Description
0	Disables multiple PFC pause quantums.
1	Enables multiple PFC pause quantums, one per pause priority.

Bit 24 – OSSMODE One Step Sync Mode

Value	Description
0	1588 One Step Sync mode is disabled.
1	1588 One Step Sync mode is enabled. Replaces timestamp field in the 1588 header for TX Sync Frames with the current TSU timer value.

Bit 22 – STUDPOFFSET Store UDP Offset

Stores UDP/TCP offset to memory.

Value	Description
0	Normal operations.
1	The upper 16 bits of the CRC of every received frame are replaced with the offset from start of frame to the beginning of the UDP or TCP header. The lower 16 bits of the CRC are replaced with zero and reserved for future use. The offset is measured in units of 2 bytes.

Bit 20 – PTPUNIENA Detection of Unicast PTP Frames Enable

Value	Description
0	Disables detection of unicast PTP frames.
1	Enables detection of unicast PTP frames.

Bit 19 – TXLPIEN Enable LPI Transmission

When set, LPI (low power idle) is immediately transmitted.

Bit 18 – FNP Flush Next Packet

Flush the next packet from the external receive memory. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the receive memory to system memory.

Value	Description
0	No effect.
1	Flushes the next packet from the receive memory. This will only have an effect if the DMA is not currently writing a packet already stored in the receive memory to system memory.

Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame

Value	Description
0	No effect.
1	Takes the values stored in the Transmit PFC Pause Register.

Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception

Enables PFC Priority Based Pause Reception capabilities. Setting this bit enables PFC negotiation and recognition of priority-based pause frames.

Bit 15 – SRTSM Store Receive Timestamp to Memory

Value	Description
0	No effect.
1	Causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message timestamp point. Note that bit RFCS in register GMAC_NCFGR may not be set to 1 when the timer should be captured.

Bit 12 – TXZQPF Transmit Zero Quantum Pause Frame

Value	Description
0	No effect.
1	Generates a pause frame with zero quantum to be transmitted.

Bit 11 – TXPF Transmit Pause Frame

Value	Description
0	No effect.
1	Generates a pause frame to be transmitted.

Bit 10 – THALT Transmit Halt

Value	Description
0	No effect.
1	Halts transmission as soon as any ongoing frame transmission ends.

Bit 9 – TSTART Start Transmission

Value	Description
0	No effect.
1	Starts transmission.

Bit 8 – BP Back Pressure

Value	Description
0	No effect.
1	When the MAC is set in 10M or 100M Half Duplex mode, forces collisions on all received frames. Ignored in Gigabit Half Duplex mode.

Bit 7 – WESTAT Write Enable for Statistics Registers

Value	Description
0	Forces the statistics registers to be in read-only mode for normal operation mode.
1	Makes the statistics registers writable for functional test purposes.

Bit 6 – INCSTAT Increment Statistics Registers

Bit 5 – CLRSTAT Clear Statistics Registers

Value	Description
0	No effect.
1	Clears the statistics registers.

Bit 4 – MPE Management Port Enable

Set to one to enable the management port. When zero, forces GMDIO to high impedance state and MDC low.

Value	Description
0	Forces GMDIO to high impedance state and MDC low.
1	Enables the management port.

Bit 3 – TXEN Transmit Enable

Value	Description
0	Stops transmission immediately, the transmit pipeline and control registers will be cleared and the Transmit Queue Pointer register will reset to point to the start of the transmit descriptor list.
1	Enables the GMAC transmitter to send data.

Bit 2 – RXEN Receive Enable

When set, RXEN enables the GMAC to receive data. When reset frame reception stops immediately and the receive pipeline will be cleared. The Receive Queue Pointer register is unaffected.

Value	Description
0	Stops frame reception immediately and the receive pipeline will be cleared. The Receive Queue Pointer register is unaffected.
1	Enables the GMAC to receive data.

Bit 1 – LBL Loop Back Local

Value	Description
0	Normal operating mode (no loop back).
1	Connects GTX to GRX, GTXEN to GRXDV and forces Full Duplex mode. GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.

Name:	GMAC_NCR
Offset:	0x000
Reset:	0x00000000
Property:	Read/Write