62.8 GMAC Transmit Buffer Queue Base Address Register

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register. Once transmission has started, any write to the Transmit Buffer Queue Base Address Register is illegal and therefore ignored.

Note that due to clock boundary synchronization, it takes a maximum of four MCK cycles from the writing of the transmit start bit before the transmitter is active. Writing to the Transmit Buffer Queue Base Address Register during this time may produce unpredictable results.

Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted.

When the datapath is configured at 64 bits, the descriptors must be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single access. The descriptors must be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses for 32-bit datapaths.