62.7 GMAC Receive Buffer Queue Base Address Register

This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base Address Register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the “used” bits.

When the datapath is configured at 64 bits, the descriptors must be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to by using a single access. The descriptors must be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses for 32-bit datapaths.

Name:	GMAC_RBQB
Offset:	0x018
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	ADDR[29:22]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADDR[21:14]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDR[13:6]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[5:0]							RXQDIS
Access	R/W	R/W	R/W	R/W	R/W	R/W		R/W
Reset	0	0	0	0	0	0		0

Bits 31:2 – ADDR[29:0] Receive Buffer Queue Base Address

Written with the address of the start of the receive queue.

Bit 0 – RXQDIS Receive Queue Disable

Value	Description
0	Queue is enabled.
1	Queue is disabled. Used to reduce the number of active queues and should only be changed while receive is not enabled.