62.98 GMAC Flushed Received Packets Counter Register

Name: GMAC_FLRXPCR
Offset: 0x1B4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 COUNT[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 COUNT[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 15:0 – COUNT[15:0] Flushed Received Packets Count (cleared on read)

Counts the number of frames that have been flushed from the receive packet buffer memory due to one of the following reasons:

  • When partial store and forward mode is enabled and a packet is received while there is no system bus resource
  • When partial store and forward mode is enabled and a system bus error is encountered while writing the packet data to system memory.
  • When automatic discard of received packed during lack of resource is enabled (bit 24 of the DMA Configuration register) and a packet is received while there is no system bus resource.
  • When a software flush of a packet from the head of the packet buffer queue (bit 18 of the Network Control register) is performed and the DMA is not currently busy.