62.139 GMAC Interrupt Enable Register Priority Queue x

The following values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name:	GMAC_IERPQx
Offset:	0x0600 + (x-1)*0x04 [x=1..5]
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					HRESP
Access					W
Reset					–


Bit	7	6	5	4	3	2	1	0
	TCOMP	TFC	RLEX			RXUBR	RCOMP
Access	W	W	W			W	W
Reset	–	–	–			–	–

Bit 11 – HRESP System Bus Error

Bit 7 – TCOMP Transmit Complete

Bit 6 – TFC Transmit Frame Corruption Due to System Bus Error

Bit 5 – RLEX Retry Limit Exceeded or Late Collision

Bit 2 – RXUBR RX Used Bit Read

Bit 1 – RCOMP Receive Complete

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