62.43 Address Mask for RX Data Buffer Accesses Register
| Name: | GMAC_AMRX |
| Offset: | 0x0D0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MSBADDR[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSBADDRMSK[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:28 – MSBADDR[3:0] MSB of the Receive Data Buffer Address
Values used to force bits 31:28 of the receive data buffer address to a particular value when the associated enable bits stored in this register [3:0] are set.
Any changes to this register are ignored while the DMA is processing a receive packet. It only affects the next full packet to be written to external system memory.
Bits 3:0 – MSBADDRMSK[3:0] Mask of the Receive Data Buffer Address
These bits are associated directly with bits[31:28].
When bit 0 is set, the address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register.
When bit 1 is set, the address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register.
When bit 2 is set, the address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register.
When bit 3 is set, the address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register.
When these bits are clear, the associated value stored in bits 31:28 have no effect on the address used for receive data buffer accesses.
Any changes to this registerare ignored while the DMA is processing a receive packet. It only affects the next full packet to be written to external memory.