62.30 GMAC Specific Address 3 Top Register

The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.

Name:	GMAC_SAT3
Offset:	0x09C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			FILTBMASK[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
								FILTSORD
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	ADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 29:24 – FILTBMASK[5:0] Filter Bytes Mask

Selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame.

Value	Name	Description
0x1	BIT1	Controls whether the first byte has been received.
0x2	BIT2	Controls whether the second byte has been received.
0x4	BIT3	Controls whether the third byte has been received.
0x8	BIT4	Controls whether the fourth byte has been received.
0x10	BIT5	Controls whether the fifth byte has been received.
0x20	BIT6	Controls whether the sixth byte has been received

Bit 16 – FILTSORD Filter Source or Destination MAC Address

Selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame.

Value	Description
0	The filter is a destination address filter.
1	The filter is a source address filter.

Bits 15:0 – ADDR[15:0] Specific Address 3

The most significant bits of the destination address, that is, bits 47:32.