62.129 GMAC Transmit Queue Upper Buffer Address Register

Name:	GMAC_TQUBA
Offset:	0x4C8
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	TQUBA[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TQUBA[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TQUBA[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TQUBA[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – TQUBA[31:0] Transmit Queue Upper Buffer Address

Upper 32 bits of transmit buffer descriptor queue base address.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.