62.21 GMAC Interrupt Moderation Register
| Name: | GMAC_INTM |
| Offset: | 0x05C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXINTMOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXINTMOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:16 – TXINTMOD[7:0] Transmit Interrupt Moderation
Count of 800 ns periods before bit 7 is set in GMAC_ISR.TCOMP. A non-zero value indicates transmit interrupt moderation will be performed.
Bits 7:0 – RXINTMOD[7:0] Receive Interrupt Moderation
Count of 800 ns periods before bit 1 is set in GMAC_ISR.RCOMP. A non-zero value indicates receive interrupt moderation will be performed.