20.2.6.3.1 WDOG_RESET_N

The WDOG_BLOCK_RESET_N signal is synchronized on M3_CLK and CLK_RCOSC, then gated with WDOG_ENABLE. The gating ensures that if WDOG_ENABLE is not asserted, WDOG_RESET_N is asserted. This reset is used to hold the watchdog logic clocked by M3_CLK in reset. The WDOG_ENABLE bit is in the watchdog configuration register (WDOG_CR as defined in Table 20-4) of the SYSREG.

The following figure shows the generation of WDOG_RESET_N.

Figure 20-18. WDOG_RESET_N Generation

The Reset Controller drives the reset input of the Watchdog Timer.