2.5.1.3.5 Program Status Register
The Program Status Register (PSR) combines:
- Application Program Status Register (APSR)
- Interrupt Program Status Register (IPSR)
- Execution Program Status Register (EPSR)
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are shown in the following figure.
![](GUID-02901B43-C97E-492B-B163-4BE33B2D9EAD-low.png)
Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:
- Read all of the registers using PSR with the MRS instruction.
- Write to the APSR using APSR with the MSR instruction.
The following table shows the PSR combinations and attributes.
Register | Type | Combination |
---|---|---|
PSR | RW1,2 | APSR, EPSR, and IPSR |
IEPSR | RO | EPSR and IPSR |
IAPSR | RW1 | APSR and IPSR |
EAPSR | RW2 | APSR and EPSR |
Note:
- The processor ignores writes to the IPSR bits.
- Reads of the EPSR bits return zero, and the processor ignores writes to the these bits.
See the instruction descriptions in 2.6.10.6 MRS and 2.6.10.7 MSR for more information about how to access the program status registers.