2.5.1.3.10 CONTROL Register

The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. For information about its attributes, see the register summary in Table 2-2. The following figure shows the bit assignments for MSR or MRS access.

Figure 2-6. Control Register
Table 2-10. Control Register Bit Assignments
BitsNameFunction
[31:2]—Reserved
[1]Active stack pointerDefines the currently active stack pointer:
  • 0: MSP is the current stack pointer
  • 1: PSP is the current stack pointer

In Handler mode this bit reads as zero and ignores writes.

[0]Thread mode privilege levelDefines the Thread mode privilege level:
  • 0: Privileged
  • 1: Unprivileged

Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value, see Table 2-17.

In an OS environment, Arm recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:

  • Use the MSR instruction to set the Active stack pointer bit to 1, see 2.6.10.7 MSR
  • Perform an exception return to Thread mode with the appropriate EXC_RETURN value. For more information, see Table 2-17
    Important: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer. For more information, see 2.6.10.5 ISB.