2.5.1.3.8 Execution Program Status Register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction

For the EPSR attributes, see the register summary in Table 2-2. The following table lists the bit assignments.

Attempts to read the EPSR directly using the MRS instruction always return zero. Attempts to write the EPSR using the MSR instruction are ignored.

Interruptible-continuable Instructions

When an interrupt occurs during the execution of an LDM, STM, PUSH, or POP instruction, the processor:

• Stops the load multiple or store multiple instruction operation temporarily
• Stores the next register operand in the multiple operation to EPSR bits[15:12]

After servicing the interrupt, the processor:

• Continues loading the register pointed to by bits[15:12]
• Resumes execution of the multiple load or store instruction

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

• If-Then Block

  The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. For more information, see 2.6.9.3 IT.

• Thumb State
  The Cortex-M3 processor only supports execution of instructions in Thumb state. The following can clear the T bit to 0:

  • Instructions BLX, BX and POP{PC}
  • Restoration from the stacked xPSR value on an exception return
  • Bit[0] of the vector value on an exception entry or reset

Attempting to execute instructions when the T bit is 0 results in a fault or lockup. For more information, see 2.5.4.4 Lockup.

The T bit can be modified both by software, using the mechanisms described in this section, and directly by the debugger.