2.5.1.3.9 Exception Mask Registers

The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks.

To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. For more information, see 2.6.10.6 MRS, 2.6.10.7 MSR, and 2.6.10.2 CPS.

Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. For information about its attributes, see the register summary in Table 2-2. The following figure for bit assignments for MSR or MRS access.

Table 2-7. PRIMASK Register Bit Assignments
Bits	Name	Function
[31:1]	—	Reserved
[0]	PRIMASK	0: no effect 1: prevents the activation of all exceptions with configurable priority.

Fault Mask Register

The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). For information about its attributes, see the register summary in Table 2-2.

The following table lists the big assignments for MSR or MRS access.

Table 2-8. FAULT Register Bit Assignments
Bits	Name	Function
[31:1]	—	Reserved
[0]	FAULTMASK	0: no effect 1: prevents the activation of all exceptions except for NMI.

The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.

Base Priority Mask Register

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. For information about its attributes, see the register summary in Table 2-2.

The following table lists the big assignments for MSR or MRS access.

Table 2-9. BASEPRI Register Bit Assignments
Bits	Name	Function
[31:8]	—	Reserved
[7:0]	BASEPRI¹	Priority mask bits: 0x00: no effect Nonzero: defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI.

Note: ⁽¹⁾ This field is similar to the priority fields in the interrupt priority registers. The device implements only bits[7:M] of this field, bits [M-1:0] read as zero and ignore writes. For more information, see 2.7.1.8 Interrupt Priority Registers. Remember that higher priority field values correspond to lower exception priorities.