20.2.6.4.2 FIC_2_APB_M_PRESET_N

This is an APB reset signal to the FPGA fabric interface.

SYSRESET_N is synchronized on FIC_2_APB_M_PCLK generated in the MSS CCC, which is driven to the FPGA fabric and then the synchronized reset is again flopped on the negative edge of M3_CLK.

The following figure shows the generation of FIC_2_APB_M_PRESET_N.

Figure 20-19. FIC_2_APB_M_PRESET_N Generation

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