12.4.5 Baud Rate Registers (DLR, DMR, and DFR)

Table 12-8. DLR
Bit NumberNameR/WReset ValueDescription
[7:0]DLRR/W0x01This divisor latch LSB register (Table 12-8) holds the LSB of the integer divisor value used to calculate the baud rate. The baud rate can be calculated using EQ 1, 2, 3, or 4.
Table 12-9. DMR
Bit NumberNameR/WReset ValueDescription
[7:0]DMRR/W0x00This divisor latch MSB register (Table 12-9) holds the MSB of the integer divisor value used to calculate the baud rate. The baud rate can be calculated using EQ 1, 2, 3, or 4.
Table 12-10. DFR
Bit NumberNameR/WReset ValueDescription
[5:0]DFRR/W0x00The fractional divisor register (Table 12-10) is used to store the fractional divisor used to calculate the fractional baud rate value in 1/64th.

0x0: 0/64

0x1: 1/64

….

0x3F: 63/64

As explained earlier, the divisor value has an integer part and a fractional part. Calculate the 6-bit number (k) which is the fractional divisor in Table 12-10 register by taking the fractional part of the required baud rate divisor and multiplying it by 64 (that is, 2n, where n is the fractional part which is 6) and adding 0.5 to account for rounding errors:

k = integer (fractional part of divisor value × 2n + 0.5)

For example, to generate the baud rate of 134.5 the reference clock is 18.432 MHz.

FAPBCLK = 18.432 MHz, Fractional BR = 134.5,
Hence, calculate the divisor value = (18.432 × 106) / (16 × 134.5) = 8,565.05

The integer part of divisor = 8565 and fractional part of divisor = 0.05

Therefore, the fractional part, k = integer ((0.05 × 64) + 0.5) = 3.7 ~ = 4

The following table contains the list of baud rates and corresponding values of DFR and DMR+DLR registers.

Table 12-11. Baud Rates and Divisor Values for the 18.432 MHz Reference Clock
Baud RateDivisorDLR + DMR Integer DivisorDFR Fractional Divisor in 64thPercent Error
5023,04023,04000.00000%
7515,36015,36000.00000%
11010,472.7210,472470.00007%
134.58,565.058,56540.00008%
1507,6807,68000.00000%
2,00057657600.00000%
38,400303000.00000%
56,00021.5721370.03255%