3.2.3.3.1 Accessing I and D Buses Concurrently

Accessing the I and D buses concurrently are not allowed. In rare cases, accessing the I and D buses concurrently might result in an invalid value returned to the internal registers from the cache causing the firmware to not function properly. To overcome this behavior, there are few workarounds such as turning off the cache, avoiding D-Bus literals, and moving variables including constants to eSRAM.

IAR tool chain users can do a work around for this problem by preventing the Cortex-M3 processor from issuing concurrent I and D buses access through the cache. To implement this work-around, updates are required to the IAR tool chains. All libraries must be fully rebuilt from the source code to avoid this interaction by preventing the cache D-Bus accesses. The user's linker scripts are required to locate constants and data variables outside the memory regions accessed by the cache to prevent conflicts. Consequently, IAR compilation requires using the -no_literal_pool option to prevent the compiler/assembler from locating variables close to instructions known as literal pools. Refer to the following two figures. This option prevents literal pool data generation of instructions that used D-bus accesses.