4.2.6 Error Response

The error response, which is indicated by the HRESP signal, is asserted if any of the following conditions occur:

• AHBL burst read is terminated early or address sequence is not as expected. This should never occur within the system during normal operation.
• AHBL write transaction addressed to read-only user data array
• AHBL read or write transaction to a protected memory area. Refer to 4.3 Security.

Data on HRDATA with error response is zero. A write transaction addressed to read-only Control register such as RD or RDT will not trigger an error response. However, the data in these registers will not be affected.