4.2.7 Interrupt to Cortex-M3 Processor

Setting the Control registers Table 4-24, as shown in Table 4-20, allows the user to configure HINT (INTISR[17] and INTISR[18] of Cortex-M3 processor) to assert an interrupt on any active status events from eNVM, such as the assertion of any status bit from eNVM or when an internal eNVM operation ends.

After HINT is asserted, the Cortex-M3 processor determines the next steps. The Cortex-M3 processor can respond to the interrupt and then clear HINT by writing 1 to bit 0 of the write-only register Table 4-25 (HADDR = 0x158) in Table 4-20. If the Cortex-M3 processor decides to ignore the interrupt (by masking it out), the interrupt is cleared if read or write continues and the interrupt-triggering events are not re-occurring. If the same triggering event happens again, HINT will remain asserted.