4.2.5 eNVM Command Register

The following table shows the Command register bit definitions.

The Command register is located at offset 0x148 in the Control register. Refer to Table 4-6 for more information. By writing to CMD when HADDR[18:0] = 0×148, any eNVM operation may be invoked. The eNVM goes into a busy state and HREADY is set High until it finishes the write operation. Any further invoking of the eNVM operation will cause HREADY to go Low until it finishes the previous operation.

Before using the eNVM read command, ensure to check the ready bit of the ENVM_SR register. The value 0 of the ready bit indicates that the eNVM controller is not busy. To execute eNVM reads/writes via FIC, ensure that the HREADY signal is LOW.

The following steps describe when to write to the Command Register, decoding of commands and command execution.

• The command register should only be written when the NVM is non-busy (Status Register bit 0). Refer to Table 4-21 for the Status Register definitions
• If the Command register is written when the NVM is still busy from a previous command then the logic will prevent the new command and all future commands, the access_denied bit in the STATUS register will be set. To recover from this state, 1 should be written to bit 1 in the Table 4-25 register to clear the access_denied bit. This mechanism is used to detect the improper NVM command sequences and protect the NVM data until the firmware recovers.
• When the AHBL triggers a write transaction with HADDR[18:0] = 0×148, HWDATA is treated as a command (CMD).
• CMD[31:24] will be decoded as the eNVM operation, as mentioned in Figure 4-4.
• The value from CMD[23:3] will be decoded as the NVM array address for the eNVM operation. Depending on the command code, some LSB bits of CMD[23:0] will be ignored. For example, to submit a program address, only the page address CMD[17:7] is significant. Therefore CMD[17:7] is taken as the NVM address and CMD[6:0] is ignored. Refer to Table 4-6 for more information.

For masters, which are only capable of byte access, four cycles of write may be needed to fill the Command (CMD) register, by writing to 0×14b, 0×14a, 0×149, and 0×148.