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SmartFusion 2 Microcontroller Subsystem
SmartFusion 2 Microcontroller Subsystem
  1. Home
  2. 4 Embedded NVM (eNVM) Controllers
  3. 4.2 Functional Description
  4. 4.2.3 eNVM Access Time

  • Introduction
  • 1 Cortex-M3 Processor Overview and Debug Features
  • 2 Cortex-M3 Processor (Reference Material)
  • 3 Cache Controller
  • 4 Embedded NVM (eNVM) Controllers
    • 4.1 Features
    • 4.2 Functional Description
      • 4.2.1 Memory Organization
      • 4.2.2 Data Retention Time
      • 4.2.3 eNVM Access Time
      • 4.2.4 Theory of Operation
      • 4.2.5 eNVM Command Register
      • 4.2.6 Error Response
      • 4.2.7 Interrupt to Cortex-M3 Processor
    • 4.3 Security
    • 4.4 How to Use eNVM
    • 4.5 SYSREG Control Registers
    • 4.6 eNVM Control Registers
  • 5 Embedded SRAM (eSRAM) Controllers
  • 6 AHB Bus Matrix
  • 7 High Performance DMA Controller
  • 8 Peripheral DMA
  • 9 Universal Serial Bus On-The-Go Controller
  • 10 Ethernet MAC
  • 11 CAN Controller
  • 12 MMUART Peripherals
  • 13 Serial Peripheral Interface Controller
  • 14 Inter-Integrated Circuit Peripherals
  • 15 MSS GPIO
  • 16 Communication Block
  • 17 RTC System
  • 18 System Timer
  • 19 Watchdog Timer
  • 20 Reset Controller
  • 21 System Register Block
  • 22 Fabric Interface Interrupt Controller
  • 23 Fabric Interface Controller
  • 24 APB Configuration Interface
  • 25 Error Detection and Correction Controllers
  • 26 Revision History
  • Microchip FPGA Support
  • Microchip Information

4.2.3 eNVM Access Time

Refer to the Embedded NVM (eNVM) Characteristics section from IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet for eNVM Maximum Read Frequency and eNVM Page Programming Time.

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