13.2.4.2.1 Processor Controlled Mode

In this mode, the size of the data frames (set in register Table 13-10) and their numbers (set in the Table 13-9[TXRXDFCOUNT] field) are specified. The data frame size specifies the number of bits being shifted out or being received per-frame. On completing each transfer, after a specified number of data frames (1 by default) are sent, an optional interrupt is generated. The SPI controller keeps track of the number of data frames so that special signals, like output enable, can be deactivated at the end of a transfer.

For example, to transmit one 17-bit word, the data frame size is set to 17, and the number of data frames is set to 1. Then depending on the operating mode, the 17 bits are transferred and the TXDATSENT Table 13-11 register bit (0) is set. If enabled, an interrupt is also generated.

For example, consider the transmission of 64 KB of data to an external EEPROM from the processor controlled SPI controller. The data frame size is set to eight and the number of data frames per-transfer is set to one. After each transfer, the software must respond to the interrupt-transmit done-and-reload the FIFO until the 64 KB of data is sent. To improve throughput, the number of data frames per each transfer can be set to 4 to utilize the full depth of the transmit FIFO.