23.7.1.2.1 Master/AHB-Lite

Instantiate and configure the CoreAHBLite bus as follows:

1. Select the Memory Space option that matches requirements:
   • If less than 16 MB of address space is required for all peripherals, select the option as shown in the following figure. This mode provides sixteen, 16 MB slots that can be used to connect up to sixteen AHB-Lite slaves.

     

   • If more than 16 MB and less than 256 MB of address space is required for any peripheral, select the option shown in the following figure. This mode provides sixteen, 256 MB slots that can be used to connect up to sixteen AHB-Lite slaves.

     

2. Enable the slots planned to be used for the application. The best practice is to use the M1 to slot accesses, as shown in the following figure.

   

   Important:

   • Use M1 if you plan to create a multi-master subsystem where you have a master in the fabric that requires the remap feature and thus needs to be connected to M0.
   • If you have selected the 16 MB per slot option, there are no restrictions on which slots can be used.
   • If you have selected the 256 MB per slot option, only the slots compatible with the FIC instance fabric memory address regions selection can be used. Each FIC memory address region is 256 MB in size. The six FIC memory regions are summarized in the following table.

     Table 23-5. Address Regions and Compatible Slots for 256 MB per Slot Option

     Memory Address Region	Compatible Slots
     30000000-3FFFFFFF	3
     50000000-5FFFFFFF	5
     70000000-7FFFFFFF	7
     80000000-8FFFFFFF	8
     90000000-9FFFFFFF	9
     F0000000-FFFFFFFF	15

3. Instantiate and configure AHB-Lite compliant peripheral cores and/or custom AHB-Lite compliant components.
4. Connect the subsystem together; this can be done in two ways:
   • Automatic Connection: Right-click in the top-level SmartDesign canvas and select the Auto Connect option. This connects the FPGA fabric peripherals to the MSS FIC interfaces through the CoreAHBLite bus and CoreAPB3 bus.
   • Manual Connection:
     • Connect the CoreAHBLite mirrored-master bus interface (BIF) port M1 to the MSS master BIF port (FIC_0/1_AHB_MASTER), as shown in the following figure.
     • Connect the AHB-Lite slaves to the proper slots as per your memory map requirement.
     • Clocks and resets; refer to the 23.7.2 Configuring the FIC Subsystem Clocks and 23.7.3 Configuring the FIC Subsystem Reset.