23.7.1.1 Step 1: Configure the MSS FIC Sub-Block

As shown in the following figure, the FIC configurator (applies to both FIC_0 and FIC_1) is organized as follows. In the left panel, the following can be configured:

  • The MSS to the FPGA fabric interface
  • Advanced AHB-Lite options
  • The FPGA fabric address regions (MSS master view) – available in FIC_0 configurator only

In the right panel, a dynamic picture displays the high level block diagram of the architecture chosen. The picture changes when any option in the MSS to FPGA fabric interface group is configured.

Figure 23-13. FIC Configurator