6.1.4.11 Memory Security
After reset, all master ports on the AHB bus matrix are enabled. There are separate user-defined Flash configuration bits that control read and write access for each memory slave from various masters, which are organized in groups. The pairing of the masters and the slaves with respect to the bits set in the security registers are given in detail in the following table. Read access and write access can be independently controlled by separate read and write Flash bits. For more information on bit configuration of S registers, see 21 System Register Block.
| SYSREG Register | Masters | Slaves | ||||
|---|---|---|---|---|---|---|
| MS0 | MS1 | MS2 | MS3 | MS6 | ||
| eSRAM0 | eSRAM1 | eNVM_0 | eNVM_1 | MSS DDR Bridge | ||
| MM0_1_2_SECURITY | MM0: M3 DCode bus, cache | RW | RW | RW | RW | RW |
| MM1: M3 ICode bus | RW | RW | RW | RW | RW | |
| MM2: M3 system bus | RW | RW | RW | RW | RW | |
| MM4_5_FIC64_SECURITY | MM4: FIC_0 | RW | RW | RW | RW | RW |
| MM5: FIC_1 | RW | RW | RW | RW | RW | |
| DDR_FIC | RW | RW | RW | RW | RW | |
| MM3_6_7_8_SECURITY | MM3: HPDMA | RW | RW | RW | RW | RW |
| MM6: MAC | RW | RW | RW | RW | RW | |
| MM7: PDMA | RW | RW | RW | RW | RW | |
| MM8: USB | RW | RW | RW | RW | RW | |
| MM9_SECURITY | MM9: System controller | RW | RW | RW | RW | RW |
An access attempt by a master where the corresponding master port is blocked (by a Flash configuration bit setting) causes the AHB bus matrix to assert HRESP to the master and terminate the transaction. If a blocked port is attempting a read access, the read data is returned as garbage. If the blocked port is attempting a write, the write of data does not occur to any slave. In both cases, one of the SW_ERRORSTATUS bits is asserted. DDR_FIC is not part of the AHB bus matrix but can be blocked from accessing the MSS DDR (MDDR) subsystem.