6.1.4.3 DDR Memory Map

Although up to 4 Gbytes of DDR is supported by the system, only 1 GB of this is accessible at one time from the Cortex-M3 processor or MSS masters via the AHB bus matrix. The HPDMA and DDR_FIC can access all 4 Gbytes at default settings. To make a particular region of DDR visible to the Cortex-M3 processor firmware or another non-HPDMA MSS master, it is necessary to configure the appropriate DDR mapping registers in the MSS system registers.