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SmartFusion 2 Microcontroller Subsystem
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6
AHB Bus Matrix
6.1
Functional Description
6.1.4
System Memory Map
6.1.4.2
eNVM Remap
Introduction
1
Cortex-M3 Processor Overview and Debug Features
2
Cortex-M3 Processor (Reference Material)
3
Cache Controller
4
Embedded NVM (eNVM) Controllers
5
Embedded SRAM (eSRAM) Controllers
6
AHB Bus Matrix
6.1
Functional Description
6.1.1
Architecture Overview
6.1.2
Timing Diagrams
6.1.3
Details of Operation
6.1.4
System Memory Map
6.1.4.1
eSRAM Remap
6.1.4.2
eNVM Remap
6.1.4.2.1
eNVM Remap for Cortex-M3
6.1.4.2.2
eNVM Remap for Soft Processor
6.1.4.3
DDR Memory Map
6.1.4.4
DDR Remap
6.1.4.5
Unimplemented Address Space
6.1.4.6
Burst Support
6.1.4.7
Locked Transactions
6.1.4.8
Peripheral Bit-Banding
6.1.4.9
Fabric Memory Map
6.1.4.10
Firmware Considerations
6.1.4.11
Memory Security
6.2
How to Use AHB Bus Matrix
6.3
Register Map
7
High Performance DMA Controller
8
Peripheral DMA
9
Universal Serial Bus On-The-Go Controller
10
Ethernet MAC
11
CAN Controller
12
MMUART Peripherals
13
Serial Peripheral Interface Controller
14
Inter-Integrated Circuit Peripherals
15
MSS GPIO
16
Communication Block
17
RTC System
18
System Timer
19
Watchdog Timer
20
Reset Controller
21
System Register Block
22
Fabric Interface Interrupt Controller
23
Fabric Interface Controller
24
APB Configuration Interface
25
Error Detection and Correction Controllers
26
Revision History
Microchip FPGA Support
Microchip Information
6.1.4.2 eNVM Remap
The following sections describe remapping eNVM.
