6.1.4.4 DDR Remap

In default mode, the Cortex-M3 processor firmware boots from eNVM. However, as shown in the following figure, it is also possible to get the firmware to boot from DDR by re-mapping DDR to location zero. Code shadowing is supported to facilitate this. User boot firmware, located in eNVM, must copy an executable image from external Flash memory (serial or parallel) to external DDR memory, then jump to the application entry point in external DDR memory.

In DDR remap mode, the total available cacheable region (512 Mbytes) can be configured to 128 Mbytes, 256 Mbytes, or 512 Mbytes. In the case of a 128 Mbyte cacheable size, the entire 512 Mbytes is divided into four cacheable regions of 128 Mbytes each, and one of the four regions will be selected as per configuration. Similarly for 256 Mbytes, one of the two cacheable regions (512 Mbytes cacheable region split to two 256 Mbyte regions) will be selected as per configuration. These selections can be configured using the DDRB_NB_ADDR_CR and DDRB_NB_SIZE_CR registers.

The cache controller generates the appropriate DDR address as per remap before putting the access request to the MSS DDR bridge. A soft SDRAM memory controller implemented in the fabric can be remapped to address 0 just like the MDDR so that external code located in SDRAM is cacheable.