6.1.4.1 eSRAM Remap

The AHB bus matrix supports remapping the eSRAM address space into code space that the Cortex-M3 processor can use. Both eSRAM blocks can be remapped to appear at the bottom of the Cortex-M3 processor code space, as shown in the preceding figure.

The amount of space available to 
Cortex-M3 processor as code space depends on ECC as indicated below:

  • When ECC is ON, the two eSRAM blocks (64 KB) can be remapped, but ECC sections of eSRAM (8 KB) cannot be used by the Cortex-M3 processor.
  • When ECC is OFF, the two eSRAM blocks (64 KB) can be remapped, and the ECC sections of eSRAM (8 KB) can also be used by the Cortex-M3 processor. These 8 KB are available at a different address. The resultant memory map is illustrated in the following figure.
Figure 6-13. Memory Map after eSRAM Remap (64 KB eSRAM)

In default mode, the Cortex-M3 processor firmware boots from eNVM. However, as shown in the preceding figure, it is also possible to get the firmware to boot from eSRAM by re-mapping eSRAM to location zero. Code shadowing is supported to facilitate this.

A master in the FPGA fabric must extend the assertion of reset to the Cortex-M3 processor until the system reset to the remainder of the MSS is negated. This master must then copy the appropriate code from eNVM to eSRAM and release the reset of the Cortex-M3 processor.