6.1.4.10 Firmware Considerations

The following must be considered while implementing Fabric logic:

• Configuring the AHB bus matrix: For the mode changes (change of protection region, memory map mode, programmable weights, and programmable maximum latency), user firmware must take care that all the masters are in IDLE state (where no data transfer is required) for a sufficient amount of time—10 IDLE cycles (ten clock cycles)—before and after the mode change.
• HBURST support in eNVM slave: HBURST is supported for an IC bus master to eNVM slaves only. SW_WEIGHT_IC of MASTER_WEIGHT0_CR is configured such that the value of SW_WEIGHT_IC is equal to or greater than the number of bursts. For example, for a burst of 8, the SW_WEIGHT_IC must be at least 8 or greater than 8.
• Avoid using infinite firmware loops in eSRAM which result in preventing WRR masters from accessing the eSRAM. A typical example is a tight polling loop in the Cortex-M3 processor firmware, executing code from eSRAM, which is polling a location in the same eSRAM and consuming its full bandwidth, thereby not allowing a lower-priority master (such as, Ethernet MAC) to access the eSRAM to perform the write of the data for which the polling loop is waiting. This leads to a hung system. 
This is due to the use of the fixed priority for processor masters in the arbitration algorithm and the possibility of eSRAM being used for both instruction fetches (I and D busses) and data accesses (SBus). It is recommended that the Cortex-M3 processor firmware is stored in a separate eSRAM from the data storage of other services.