10.4.2 Receive Operation

  1. Before any packets are received, a group of Rx descriptors needs to be set up to define the ring buffer used for receive operations.

    The start addresses set for the different segments of the ring buffer are required to be word-aligned and should be spaced to give segments of equal size, each able to handle a packet of the maximum size to be transferred.

    The packet size components of these descriptors should initially be written to have ‘1’ in bit 31, which is the empty flag to indicate that the ring buffer does not currently contain any received packets.

  2. Bits [7:4] of the DMA Interrupt Mask register are set to specify which Rx DMA events cause a DMA interrupt to be generated.
  3. The location of the descriptor corresponding to the entry point in the Rx ring buffer should be written to the DMA Rx descriptor register and to enable the DMA transfer of receive packets enabled by writing a ‘1’ the bit 0 of DMA Rx control register which is the RxEnable bit.

  4. The built-in DMA controller then reads DMA Rx descriptor to discover the location of the first Rx descriptor. The built-in DMA controller then reads that descriptor to check that the associated area of the host memory is available for storing the received packet. This is indicated by the empty flag in bit 31 of the PacketSize component of the descriptor and the start address of this storage area.

    If the Empty Flag is ‘0’, this suggests that the storage area already contains a packet that has not yet been read by the host software.

    When the Empty flag is ‘0’, the DMA controller terminates the sequence of the receive packet transfers, sets the RxOverflow bit in the DMA_RX_STATUS register and clears the RxEnable bit in the DMA_RX_CTRL register.

    If enabled, an interrupt is generated with the DMA Interrupts register showing RxOverflow as the source of this interrupt. Any further transfers require the DMA_RX_DESC register to be updated to record the start position in the ring buffer that is now required and the RxEnable bit to be set to '1' again.

  5. Transfer starts when FIFO indicates that there is a packet waiting to be transferred.

  6. If the transfer is completed successfully, the DMA controller records the number of bytes transmitted in bits [11:0] of the PacketSize component of the descriptor and writes ‘0’ in bit 31 to record that a packet has been stored in the ring buffer.

    The RxPktReceived flag in the DMA_RX_STATUS register is also to be set (if not already set), the RxPktReceived interrupt is to be generated (if enabled) and the RxPktCount is recorded in 
bits[23:16] of that register incremented by 1.

  7. The DMA controller then moves on to transfer the next packet in the next segment of the ring buffer. The location of the descriptor associated with the next segment in the ring has already been read from the NextDescriptor component of the current descriptor.
  8. The software should respond to the RxPktReceived interrupt by reading the packet from its location in the ring buffer and then setting the Empty Flag in the descriptor to ‘1’ again to mark this segment of the ring buffer as available for storing further received packets.
  9. If a bus error occurs, the DMA controller terminates the sequence of the receive packet transfers, sets the Bus Error bit in the DMA_RX_STATUS register, and clears the RxEnable bit in the DMA_RX_CTRL register. If enabled, an interrupt is generated with the DMA Interrupts register showing an Rx Bus Error as the source of this interrupt.

    Any further transfers require the DMA_RX_DESC register to be updated to record the start position in the ring buffer that is now required and the RxEnable bit is to be set to ‘1’ again.