10.4.1 Transmit Operation

  1. Before any packet can be transmitted, a group of Tx descriptors needs to be set up to define the ring buffer used for transmit operations.

    The start addresses set for the different segments of the ring buffer are required to be word aligned and should be spaced to give segments of equal size, each able to handle a packet of the maximum size to be transferred.

    The packet size component of transmit descriptors should initially be written to have ‘1’ in bit 31, which is the empty flag to indicate that the ring buffer does not currently contain any valid data.

  2. The least significant four bits of the DMA interrupt mask register are set to specify which Tx DMA events cause a DMA interrupt to be generated.
  3. The data for one or more transmit packets should then be placed in contiguous segments of the ring buffer. The PacketSize component of the descriptor associated with these segments amended both to record the size of the packet placed in the buffer and to set the Empty Flag to ‘0’ to indicate the presence of valid data.
  4. The location of the descriptor, which acts as the entry point in the Tx ring buffer, is written in the DMA Tx descriptor register.The DMA transfer of the transmit packets are enabled by writing a ‘1’ to the bit 0 of the DMA Tx control register, which is Tx enable bit.
  5. The built-in DMA controller then reads the DMA Tx descriptor register to discover the location of the first Tx descriptor. The Tx descriptor is read to check the validity of the associated packet which is indicated by the empty flag, the start address of the packet to be transmitted, and its size.

    If the empty flag is ‘1’ then the descriptor is not associated with valid data. The DMA controller terminates the sequence of transmit packet transfers, set the TxUnderrun bit in the DMA Tx Status register and clear the TxEnable bit in the DMA Tx Control register. The TxUnderrun bit in the DMA Tx Status register is set whenever DMA controller reads a ‘1’ in the empty flag of the Tx Descriptor being processed.

    If the empty flag is ‘1’, the DMA terminates the transmit operation and then an interrupt is generated for TxUnderrun if enabled. The DMA interrupts register shows TxUnderrun as the source of this interrupt. Any further transfers require the DMA Tx descriptor register to be updated to record the start position in the ring buffer and to set the TxEnable bit to ‘1’ again.

  6. The transfer starts when the FIFO indicates that there is a space in the FIFO for a packet of the maximum packet size.
  7. If the transfer is completed successfully, the DMA controller writes ‘1’ to bit 31 of the PacketSize component of the descriptor. The TxPktSent flag in the DMA_TX_STATUS register needs to be set (if not already set), the TxPktSent interrupt is to be generated (if enabled) and the TxPktCount is recorded in bits [23:16] of the DMA_TX_STATUS register incremented by 1.
  8. The DMA controller then moves on to process any packet stored in the next segment of the ring buffer. The location of the descriptor associated with the next segment in the ring has already been read from the NextDescriptor component of the sequence of transmit packet transfers, sets the Bus Error bit in the DMA_TX_STATUS register, and clears the TxEnable bit in the DMA_TX_CTRL register. If enabled, an interrupt is generated with the DMA Interrupts register showing a Tx Bus Error as the source of this interrupt.

    
Any further transfers require the DMA_TX_DESC register to be updated to record the new start position in the ring buffer and the TxEnable bit to be set to ‘1’ again.