13.2.2.3.2 Output Enable (SPI_X_DOE_N) Timing

Each SPI mode comprises two phases: transmit and receive. It is a requirement that the output enable (SPI_X_DOE_N) line, which enables the output signal, should be driven so that the following occurs:

  • The output signal is ready to transmit when the data is available (setup time).
  • The output signal is held on long enough for the recipient to sample the data (hold time).

The minimum setup and hold time is one half SPI_X_CLK. In slave mode, the input clock is withdrawn at the end of the transfer. For example, consider the waveform for Single Frame Transfer – Mode 2: SPO = 1, SPH = 0. In this case, data is sampled on the falling edge of the clock and shifted on the rising edge of the clock. The data is sampled on the falling edge and must be held for one half SPI_X_CLK after the last falling edge at the end of the transmission. This means that SPI_X_DOE_N must be held High for at least one half SPI_X_CLK after the last falling edge to satisfy the hold time requirement.

Table 13-4. Behavior of the Output Enable Signal
Mode Master Slave
MOTOROLA SPI_X_DOE_N is asserted with identical timing to that of SPI_X_SS[0]. This provides an additional half SPI_X_CLK cycle of data turn on and off relative to the data bit valid requirements. The incoming SPI_X_SS[0] signal is used to directly generate the SPI_X_DOE_N. Similar to the master case, it provides an additional half clock cycle of data turn on and off.
Texas Instruments SPI_X_DOE_N is asserted on the negative clock edge prior to the MSB (while SPI_X_SS[0] is asserted) and if the uninterrupted data is deasserted on the falling SPI_X_CLK edge following the LSB. This provides half a clock cycle of data turn on off time. SPI_X_DOE_N is asserted on the positive SPI clock edge as the MSB is the output. SPI_X_DOE_N is deasserted on the positive SPI clock edge at the end of the LSB data bit, assuming no consecutive data.
National Semiconductor MICROWIRE SPI_X_DOE_N is asserted with SPI_X_SS[0], and then removed at the start of the ninth data bit (turn around cycle). SPI_X_DOE_N is asserted at the start of the tenth bit as data becomes valid. SPI_X_DOE_N is deasserted at the end of the LSB, if a falling clock edge occurs or when SPI_X_SS[0] is deasserted.