13.2.2.3.5 Devices Requiring Data Frame Sizes of More than 32 Bits

Serial Flash devices such as the Atmel AT25DF321 that support mode 3 (SPO = 1 and SPH = 1) require more than 32 bits of frame data in some modes. To drive these devices, continuous transfers are required from the SPI interface while holding the slave select low continuously (which is connected to the chip select of the target device). This is accomplished by using the transmit FIFO from the SPI, which enforces continuous back-to-back transfers, if it is not empty. The slave select continues to be held low (active) in SPI mode 3 (SPO = 1 and SPH = 1) and not pulsed between data frames.

For example, to send 64 bits to the AT25DF321 (8-bit opcode, 24-bit address, 4 data bytes), the data frame size (Table 13-10) can be set to 32 and the data frame count set to 2 (Table 13-9[TXRXDFCOUNT] field).

TXRXDFCOUNT Register

The SPI peripheral contains a TXRXDFCOUNT counter (found in the Table 13-9 register) that counts the number of transmitted and received frames. Its function varies in master and slave modes.

TXRXDFCOUNT in master mode controls the following:

  • The Tx and Rx done interrupts
  • Terminates the auto fill and empty operations
  • Holds slave select active

TXRXDFCOUNT in slave mode controls the following:

  • The Tx and Rx done interrupts
  • Terminates the auto fill operation

In slave operation, it is possible for TXRXDFCOUNT to miscount actual transmitted and received frames if the transmit FIFO under-run condition occurs. If this is likely in an application, Microchip recommends that TXRXDFCOUNT not be used and that it be disabled. Instead use the CMDINT and SSEND bits in the Raw Interrupt Status (RIS) register to monitor operation, or simply count how many frames it is received.

Page Program for Atmel AT25DF321

The following figure shows the Page Programming Timing for Atmel AT25DF321. In this mode, the opcode, address, and data require more than 32 clock periods. To drive this device, the chip select (CS) can be connected to the slave select signal, the data frame size set to 16, and the FIFO repeatedly filled until the target Flash device is programmed. As long as the data is available to transmit in the FIFO, the chip select signal (connected to slave select on the SPI controller) is asserted Low.

Figure 13-10. Page Program Timing

Devices That Do Not Support Mode 1 (SPO = 0 and SPH = 1) or Mode 3 (SPO = 1 and SPH = 1)

For Flash devices that do not support mode 1 (SPO = 0 and SPH = 1) or mode 3 (SPO = 1 and SPH = 1), it is necessary to use a dedicated GPIO pin to drive the chip select signal.