13.2.2.3.1 Motorola SPI Modes

Motorola SPI modes are shown in the following figures.

Single Frame Transfer – Mode 0: SPO = 0, SPH = 0

Figure 13-3. Motorola SPI Mode 0

Multiple Frame Transfer – Mode 0: SPO = 0, SPH=0

Figure 13-4. Motorola SPI Mode 0 Multiple Frame Transfer
Important:
  • Between frames, the slave select (SPI_SS[x]) signal is asserted for the duration of the clock pulse.
  • Between frames, the clock (SPI_CLK) is Low.
  • Data is transferred to Most Significant Bit (MSB) first.
  • The output enable (SPI_DOE_N) signal is asserted during the transmission and deasserted at the end of the transfer (after the last frame is sent).

Single Frame Transfer – Mode 1: SPO = 0, SPH = 1

Figure 13-5. Motorola SPI Mode 1

Single Frame Transfer – Mode 2: SPO = 1, SPH = 0

Figure 13-6. Motorola SPI Mode 2

Single Frame Transfer – Mode 3: SPO = 1, SPH = 1

Figure 13-7. Motorola SPI Mode 3