37.4.15 I3CxERRIE1
Note: Refer to the
I3CxERRIR1 register for the corresponding interrupt flag bits.
| Name: | I3CxERRIE1 |
| Address: | 0x091, 0x0C4 |
Error Interrupt Enable 1
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ABEIE | MWLOEIE | TXWEIE | RXREIE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – ABEIE Abort Error Interrupt Enable
| Value | Description |
|---|---|
| 1 | Abort Error Interrupt is enabled |
| 0 | Abort Error Interrupt is disabled |
Bit 2 – MWLOEIE Maximum Write Length Over Size Error Interrupt Enable
| Value | Description |
|---|---|
| 1 | Maximum Write Length Over Size Error Interrupt is enabled |
| 0 | Maximum Write Length Over Size Error Interrupt is disabled |
Bit 1 – TXWEIE Transmit Buffer Write Error Interrupt Enable
| Value | Description |
|---|---|
| 1 | Transmit Buffer Write Error Interrupt is enabled |
| 0 | Transmit Buffer Write Error Interrupt is disabled |
Bit 0 – RXREIE Receive Buffer Read Error Interrupt Enable
| Value | Description |
|---|---|
| 1 | Receive Buffer Read Error Interrupt is enabled |
| 0 | Receive Buffer Read Error Interrupt is disabled |
