37.4.11 I3CxERRIR1

Note:
  1. Will not self-clear after the event. The user must clear this bit to re-arm.
  2. In case of a race condition, user writes always take precedence over hardware events.
Name: I3CxERRIR1
Address: 0x08D, 0x0C0

Error Interrupt Flag 1

Bit 76543210 
 ABEIFMWLOEIFTXWEIFRXREIF 
Access R/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000 

Bit 3 – ABEIF  Abort Error Interrupt Flag(1)

ValueDescription
1 An In-Band Interrupt or Private Read transmission was aborted by the Controller
0 An In-Band Interrupt or Private Read transmission has not been aborted by the Controller

Bit 2 – MWLOEIF  Maximum Write Length Over Size Error Interrupt Flag(1)

ValueDescription
1 The Controller attempted to write one more byte than the Maximum Write Length size (I3CxMWL)
0 Maximum Write Length violation not occurred

Bit 1 – TXWEIF  Transmit Buffer Write Error Interrupt Flag(1)

ValueDescription
1 Invalid write occurred; I3CxTXB was written while TXBE=0
0 Invalid write not occurred

Bit 0 – RXREIF  Receive Buffer Read Error Interrupt Flag(1)

ValueDescription
1 Invalid read occurred; I3CxRXB was read while RXBF=0
0 Invalid read not occurred
Will not self-clear after the event. The user must clear this bit to re-arm. In case of a race condition, user writes always take precedence over hardware events.