37.4.27 I3CxIBIPSZ
Note:
- The Controller may update the value of this register by issuing a SETMRL CCC.
- In case of a race condition, user writes always take precedence over hardware events.
| Name: | I3CxIBIPSZ |
| Address: | 0x0A1, 0x0D4 |
In-Band Interrupt Payload Size
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IBIPSZ[7:0] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – IBIPSZ[7:0] In-Band Interrupt Payload Size
| Value | Description |
|---|---|
| other | In-Band Interrupt Payload Size (including Mandatory Data Byte) in bytes |
| 0 | Unlimited In-Band Interrupt Payload Size |