37.4.39 I3CxMRS

Note:

This register follows the definition of GETMXDS CCC Maximum Write Speed Byte format as per the MIPI I3C 1.1.1 Specification. The Controller can read this byte during GETMXDS CCC.
To ensure expected behavior, this register should only be written when the module is disabled (EN = 0).

Name:	I3CxMRS
Address:	0x0AD, 0x0E0

Maximum Read Speed


Bit	7	6	5	4	3	2	1	0
	MRS[7]	MRS[6]	MRS[5:3]			MRS[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – MRS[7] MIPI Reserved

Bit 6 – MRS[6] Stop between Write-to-Read

Value	Description
1	If I3CxMRT != 0, the Target permits Write-to-Read to be split by a Stop condition
0	If I3CxMRT !=0, the Target does not permit Write-to-Read to be split by a Stop condition. A Stop in between will cancel the Read request.

Bits 5:3 – MRS[5:3] Clock To Data Turnaround Time (T_SCO)

Value	Description
111	T_SCO > 12 ns and is reported by private agreement
110	MIPI Reserved
101	MIPI Reserved
100	≤12 ns
011	≤11 ns
010	≤10 ns
001	≤9 ns
000	≤8 ns

Bits 2:0 – MRS[2:0] Maximum Sustained Read Speed for Non-CCC Messages

Value	Description
111	MIPI Reserved
110	MIPI Reserved
101	MIPI Reserved
100	2 MHz
011	4 MHz
010	6 MHz
001	8 MHz
000	F_SCL Max

This register follows the definition of GETMXDS CCC Maximum Write Speed Byte format as per the MIPI I3C 1.1.1 Specification. The Controller can read this byte during GETMXDS CCC. To ensure expected behavior, this register should only be written when the module is disabled (EN Target Enable = 0).

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